MOS transistors and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-8980705-B2
Application number	US-201314096286-A
Country	US
Kind code	B2
Filing date	Dec 4, 2013
Priority date	Aug 5, 2013
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; and forming a ploy silicon dummy gate structure having a high-K gate dielectric layer, a high-K gate dielectric protection layer containing nitrogen and a poly silicon dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the poly silicon dummy gate structure. Further, the method includes removing the poly silicon dummy gate to form a trench exposing the high-K gate dielectric protection layer containing nitrogen and performing a nitrogen treatment process to repair defects in the high-K gate dielectric protection layer containing nitrogen caused by removing the poly silicon dummy gate. Further, the method also includes forming a metal gate structure in the trench.

First claim

What is claimed is:

1. A method for fabricating a MOS transistor, comprising:
providing a semiconductor substrate;
forming a ploy silicon dummy gate structure having a high-K gate dielectric layer on the semiconductor substrate, a high-K gate dielectric protection layer containing nitrogen on the high-K gate dielectric layer and a poly silicon dummy gate on the high-K gate dielectric protection layer on the semiconductor substrate;
forming a source region and a drain region in…

Assignees

• Semiconductor Mfg Int Shanghai

Inventors

• Li Fenglian
• Ni Jinghua

Classifications

• H10D64/01344

  Electricity · mapped topic

• H10D64/01318 Primary

  Electricity · mapped topic

• H10D62/822

  Electricity · mapped topic

• H10D30/797

  Electricity · mapped topic

• H10D30/601

  Electricity · mapped topic