Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Method of packaging semiconductor die
US8980696B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8980696-B2 |
| Application number | US-201113292103-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 9, 2011 |
| Priority date | Nov 9, 2011 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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- Title
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Abstract
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A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of packaging a semiconductor die, comprising: providing a process mounting surface having an encapsulating area; placing an embedded unit on the process mounting surface within the encapsulating area, wherein the embedded unit has a first surface, an inner surface and an outer surface, the first surface having a first opening defined by the inner surface through the embedded unit, and wherein the first surface is positioned on the process mounting…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8980696B2 cover?
- A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a pr…
- Who is the assignee on this patent?
- Meng Dominic Koey Poh, Gong Zhiwei, Muniandy Kesvakumar V C, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).