Semiconductor device manufacturing method

US8980692B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8980692-B2
Application numberUS-201414156671-A
CountryUS
Kind codeB2
Filing dateJan 16, 2014
Priority dateAug 3, 2011
Publication dateMar 17, 2015
Grant dateMar 17, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a circuit substrate, a first semiconductor chip disposed on the circuit substrate, a plurality of first spacers disposed on the first semiconductor chip, a second semiconductor chip which includes a first adhesive agent layer on a lower face thereof and is disposed on upper portions of the plurality of spacers, a wire which connects the circuit substrate to the first semiconductor chip, and a first sealing material which seals a gap between the first semiconductor chip and the first adhesive agent layer, wherein each height of the plurality of the first spacers is greater than height of the wire relative to an upper face of the first semiconductor chip.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device manufacturing method comprising: mounting a second semiconductor chip including a first adhesive agent layer, which is thermoplastic and disposed on a lower face thereof, on a spacer directly adhered to an upper face of a first semiconductor chip disposed on a circuit substrate; and adhering the second semiconductor chip to the spacer after the mounting of the second semiconductor by pressing the second semiconductor chip mounted on…

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What does patent US8980692B2 cover?
A semiconductor device includes a circuit substrate, a first semiconductor chip disposed on the circuit substrate, a plurality of first spacers disposed on the first semiconductor chip, a second semiconductor chip which includes a first adhesive agent layer on a lower face thereof and is disposed on upper portions of the plurality of spacers, a wire which connects the circuit substrate to the f…
Who is the assignee on this patent?
Fujitsu Semiconductor Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).