Hardmask composition, hardmask layer, and method of forming patterns
US-2024377746-A1 · Nov 14, 2024 · US
Method of forming an array of high aspect ratio semiconductor nanostructures
US8980656B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8980656-B2 |
| Application number | US-201013503123-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 14, 2010 |
| Priority date | Oct 21, 2009 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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Abstract
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A new method for forming an array of high aspect ratio semiconductor nanostructures entails positioning a surface of a stamp comprising a solid electrolyte in opposition to a conductive film disposed on a semiconductor substrate. The surface of the stamp includes a pattern of relief features in contact with the conductive film so as to define a film-stamp interface. A flux of metal ions is generated across the film-stamp interface, and a pattern of recessed features complementary to the pattern of relief features is created in the conductive film. The recessed features extend through an entire thickness of the conductive film to expose the underlying semiconductor substrate and define a conductive pattern on the substrate. The stamp is removed, and material immediately below the conductive pattern is selectively removed from the substrate. Features are formed in the semiconductor substrate having a length-to-width aspect ratio of at least about 5:1.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method of forming an array of high aspect ratio semiconductor nanostructures, the method comprising: positioning a surface of a stamp comprising a solid electrolyte in opposition to a conductive film disposed on a semiconductor substrate, the surface of the stamp including a pattern of relief features in contact with the conductive film so as to define a film-stamp interface, and the relief features having at least one lateral dimension of about 1 mi…
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Electricity · mapped topic
- H10P50/692Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Operations & Transport · mapped topic
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- What does patent US8980656B2 cover?
- A new method for forming an array of high aspect ratio semiconductor nanostructures entails positioning a surface of a stamp comprising a solid electrolyte in opposition to a conductive film disposed on a semiconductor substrate. The surface of the stamp includes a pattern of relief features in contact with the conductive film so as to define a film-stamp interface. A flux of metal ions is gene…
- Who is the assignee on this patent?
- Li Xiuling, Fang Nicholas X, Ferreira Placid M, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10P50/692. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).