Reducing instruction miss penalties in applications

Patent metadata

Field	Value
Publication number	US-8978022-B2
Application number	US-201313738811-A
Country	US
Kind code	B2
Filing date	Jan 10, 2013
Priority date	Jan 10, 2013
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

Embodiments include systems and methods for reducing instruction cache miss penalties during application execution. Application code is profiled to determine “hot” code regions likely to experience instruction cache miss penalties. The application code can be linearized into a set of traces that include the hot code regions. Embodiments traverse the traces in reverse, keeping track of instruction scheduling information, to determine where an accumulated instruction latency covered by the code blocks exceeds an amount of latency that can be covered by prefetching. Each time the accumulated latency exceeds the amount of latency that can be covered by prefetching, a prefetch instruction can be scheduled in the application code. Some embodiments insert additional prefetches, merge prefetches, and/or adjust placement of prefetches to account for scenarios, such as loops, merging or forking branches, edge confidence values, etc.

First claim

What is claimed is:

1. A system for reducing instruction cache miss penalties in application code execution, the system comprising:
a processor; and
a non-transient storage medium having instructions stored thereon, which, when executed, cause the processor to instantiate a compiler comprising:
a code profiler, operable to:
determine an instruction cache miss penalty for each of a plurality of code sections of application code, the instruction cache miss penalty indicating a…

Assignees

• Oracle Int Corp

Inventors

• Kalogeropulos Spiros
• Tirumalai Partha

Classifications

• G06F9/3861 Primary

  Physics · mapped topic

• G06F9/3802 Primary

  Physics · mapped topic

• G06F8/4442

  Physics · mapped topic

• G06F9/30047

  Physics · mapped topic

• G06F9/45516

  Physics · mapped topic