Log structured block device for hard disk drive
US-9851926-B2 · Dec 26, 2017 · US
Iterative decoder systems and methods
US8977941B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8977941-B2 |
| Application number | US-201414166428-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 28, 2014 |
| Priority date | Dec 6, 2007 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Abstract
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Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D 2 ) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.
First claim
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What is claimed is: 1. A method for generating encoded information, the method comprising: receiving an input signal; generating a high rate run length limited (HR RLL) encoded signal with an HR RLL encoder; generating parity bits from the HR RLL encoded signal; interleaving the parity bits with the HR RLL encoded signal to generate a parity signal; and processing the parity signal with a precoder, wherein RLL constraints are imposed on the encoded information by a combine…
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- G11B20/1426Primary
Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8977941B2 cover?
- Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decod…
- Who is the assignee on this patent?
- Marvell World Trade Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11B20/1426. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).