Registration of a PUF signature and regeneration using a trellis decoder
US-12081238-B2 · Sep 3, 2024 · US
US8977924B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8977924-B2 |
| Application number | US-201213607907-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 10, 2012 |
| Priority date | Sep 10, 2012 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.
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What is claimed is: 1. A method for decoding a LDPC encoded signal in a layered architecture, comprising: bit-shifting, with a computer processor, a first signal based on a delta shift value; selecting, with a computer processor, a signal from the bit-shifted first signal and a second combined signal, wherein the second combined signal is a combination of at least two signals; and storing the selected signal in a ping-pong memory designated for storing some combination of P ty…
Electricity · mapped topic
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