Solid-state imaging device and camera system
US-9204075-B2 · Dec 1, 2015 · US
Highly secure and extensive scan testing of integrated circuits
US8977917B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8977917-B2 |
| Application number | US-201313858422-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 8, 2013 |
| Priority date | Oct 16, 2012 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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- Title
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Abstract
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In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for restricting access to scan testing of a logic device having a programmable fabric, the method comprising the logic device: (a) receiving a set of instructions for programming the programmable fabric; (b) programming the programmable fabric based on the set of instructions; (c) deriving a multi-bit fabric pattern value from the programmed fabric; (d) processing the multi-bit fabric pattern value to determine whether or not to restrict acces…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8977917B2 cover?
- In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O in…
- Who is the assignee on this patent?
- Lattice Semiconductor Corp
- What technology area does this patent fall under?
- Primary CPC classification H03M1/34. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).