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Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency
US8977835B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8977835-B2 |
| Application number | US-201314079875-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 14, 2013 |
| Priority date | Dec 14, 2011 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Abstract
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Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.
First claim
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What is claimed is: 1. A method comprising: receiving a plurality of instructions, wherein said plurality of instructions comprises a first vector instruction and a second vector instruction, and execution of said second vector instruction depends on an execution result of said first vector instruction, executing said first vector instruction utilizing a processor functional unit, wherein said processor functional unit comprises a pipelined execution unit; determining a f…
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- G06F9/30036Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US8977835B2 cover?
- Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification G06F9/30036. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).