Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
Memory system
US8977833B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8977833-B2 |
| Application number | US-201213451750-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 20, 2012 |
| Priority date | Apr 28, 2011 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
According to one embodiment, a memory system has a data transfer device which includes a first command generating unit, a second command generating unit, a first storage unit, a second storage unit, and a nonvolatile memory managing unit. The first command generator generates a first command for reading out data from a nonvolatile memory to a host apparatus. The second command generator generates a second command for internal processing of the memory system associated with a temporary memory and the nonvolatile memory. The first memory has a queue structure configured to store the first command. The second memory has a queue structure configured to store the second command. The memory manager is configured to read out the first command stored in the first memory in priority to the second command stored in the second memory and to transmit read-out command to the nonvolatile memory.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory system comprising: a nonvolatile memory; a temporary memory; and a data transfer device configured to perform data transfer between a host apparatus and the nonvolatile memory by using the temporary memory as a buffer, wherein the data transfer device includes a first command generator configured to generate a first command for reading out data, for which a read request is issued from the host apparatus, from the nonvolatile memory, a secon…
Assignees
Inventors
Classifications
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8977833B2 cover?
- According to one embodiment, a memory system has a data transfer device which includes a first command generating unit, a second command generating unit, a first storage unit, a second storage unit, and a nonvolatile memory managing unit. The first command generator generates a first command for reading out data from a nonvolatile memory to a host apparatus. The second command generator generat…
- Who is the assignee on this patent?
- Kazui Takashi, Yoshida Norikazu, Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).