Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips

Patent metadata

Field	Value
Publication number	US-8977832-B2
Application number	US-201313933983-A
Country	US
Kind code	B2
Filing date	Jul 2, 2013
Priority date	Feb 27, 2001
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

First claim

What is claimed is:

1. A semiconductor device comprising:
a processing unit;
a memory controller configured to communicate with at least two different types of memory devices, the memory controller including:
a first interface configured to receive control output signals from the processing unit to access at least one of the memory devices,
a conversion circuit configured to covert the control output signals to memory input signals in accordance with operation specifications…

Assignees

• Fujitsu Semiconductor Ltd

Inventors

• Takemae Yoshihiro

Classifications

• G06F13/1694

  Physics · mapped topic

• G06F3/0688

  Physics · mapped topic

• G11C7/1072

  Physics · mapped topic

• G06F3/0658

  Physics · mapped topic

• G06F3/0659

  Physics · mapped topic