Combined transparent/non-transparent cache

Patent metadata

Field	Value
Publication number	US-8977818-B2
Application number	US-201314032405-A
Country	US
Kind code	B2
Filing date	Sep 20, 2013
Priority date	Jul 10, 2009
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

First claim

What is claimed is:

1. A memory unit comprising:
a tag memory configured to store a plurality of tags corresponding to a plurality of cache blocks;
a data memory configured to store data including the plurality of cache blocks, wherein the data memory is delineated into a transparent portion storing the plurality of cache blocks and a non-transparent portion that is directly mapped to a memory address range in a memory address space to which a main memory is also directly mapped…

Assignees

• Apple Inc

Inventors

• Wang James
• Chen Zongjian
• Keller James B
• Millet Timothy J

Classifications

• G06F12/0802 Primary

  Physics · mapped topic

• G06F12/125 Primary

  Physics · mapped topic

• G06F2212/601

  Physics · mapped topic

• G06F2212/2515

  Physics · mapped topic

• G06F12/0831

  Physics · mapped topic