Parallel Processing Of Data
US-2024338235-A1 · Oct 10, 2024 · US
System and method for detecting unreachable states in a statemate statechart model
US8977533B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8977533-B2 |
| Application number | US-201113023900-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 9, 2011 |
| Priority date | Feb 9, 2011 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Abstract
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The present invention provides a system and method for detecting unreachable states in a large commercial Statemate Statechart model. A system for checking the reachability of any given state in a Statemate Model, the said system comprises: an input means for receiving an Original Statemate Model (OSM), output means for displaying the result to a user, and a processor, wherein the processor is capable of executing the programmed instructions to: transform the OSM into First Statemate Model (FSM) by using translator; transform the OSM into Second Statemate Model (SSM) based on the determined length of the super step such that the set of all initial configurations of the SSM is a superset of all the stable configurations of the OSM by using translator; check the reachability of states of the OSM in the SSM by using bounded model checker (BMC); and send the result to the output means.
First claim
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What is claimed is: 1. A system for checking statuses of states in a Statemate Model using bounded model checking (BMC), the system comprises: an input means for receiving an Original Statemate Model (OSM), and a processor coupled to the input means, wherein the processor is capable of executing certain programmed instructions to: transform the OSM into a First Stalemate Model (FSM), wherein the FSM comprises a set of initial FSM configurations, and wherein the set of initial F…
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- What does patent US8977533B2 cover?
- The present invention provides a system and method for detecting unreachable states in a large commercial Statemate Statechart model. A system for checking the reachability of any given state in a Statemate Model, the said system comprises: an input means for receiving an Original Statemate Model (OSM), output means for displaying the result to a user, and a processor, wherein the processor is …
- Who is the assignee on this patent?
- Shrotri Ulka, Ramanathan Venkatesh, Metta Ravindra, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F8/433. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).