Video server and controlling method for video server

US8977100B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8977100-B2
Application numberUS-201213598083-A
CountryUS
Kind codeB2
Filing dateAug 29, 2012
Priority dateSep 16, 2011
Publication dateMar 10, 2015
Grant dateMar 10, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

According to one embodiment, a video server reads a first type of video signal for one screen from a memory address related to a screen based on a clock pulse if first information in order to read the first type of video signal from the memory device with the first predetermined time interval and the clock pulse are received, and reads a second type of video signal for integral multiple screens from the playback controller in order to read the second type of video signal from the memory device with a changing point of the clock pulse level if the second information from the playback controller in order to read the second type of video signal from the memory device with the first predetermined time interval and the clock pulse are received.

First claim

Opening claim text (preview).

The invention claimed is: 1. A video server, comprising: a memory device configured to store a first video signal with a first predetermined time interval and a second video signal with a second predetermined time interval, the second predetermined time interval being an integer division of the first predetermined time interval; a playback device configured to play back alternatively the first type of video signal and the second type of video signal from the memory device; and…

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What does patent US8977100B2 cover?
According to one embodiment, a video server reads a first type of video signal for one screen from a memory address related to a screen based on a clock pulse if first information in order to read the first type of video signal from the memory device with the first predetermined time interval and the clock pulse are received, and reads a second type of video signal for integral multiple screens…
Who is the assignee on this patent?
Kiura Kenichi, Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H04N5/93. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).