Partial block read voltage offset
US-2024071506-A1 · Feb 29, 2024 · US
US8976592B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8976592-B2 |
| Application number | US-201313804128-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 14, 2013 |
| Priority date | Apr 19, 2012 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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A nonvolatile memory device includes a flag cell configured to store flag information, a plurality of dummy cells adjacent to the flag cell, and program control logic configured to control a program operation on the flag cell and a dummy program operation on the plurality of dummy cells. When the program operation on the flag cell is performed, the program control logic performs the dummy program operation on at least one of the plurality of dummy cells.
Opening claim text (preview).
What is claimed is: 1. A nonvolatile memory device, comprising: a flag cell configured to store flag information; a plurality of dummy cells adjacent to the flag cell; and program control logic configured to control a program operation of the flag cell and a dummy program operation of the plurality of dummy cells, wherein, when the program operation of the flag cell is performed, the program control logic performs the dummy program operation of at least one of the plurality…
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