Analog sensing of memory cells in a solid-state memory device

Patent metadata

Field	Value
Publication number	US-8976582-B2
Application number	US-201113025279-A
Country	US
Kind code	B2
Filing date	Feb 11, 2011
Priority date	Jul 19, 2007
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.

First claim

What is claimed is:

1. A memory device comprising:
an array of memory cells organized in word lines and bit lines, each cell programmable to a target threshold voltage;
a sample and hold circuit for storing a representation of the target threshold voltage;
a current sensing circuit coupled between the sample and hold circuit and a bit line for detecting a bit line current in response to a read voltage on a word line; and
a comparator circuit for generating an inhibit signal…

Assignees

• Sarin Vishal
• Hoei Jung-Sheng
• Roohparvar Frankie F
• Micron Technology Inc

Inventors

• Sarin Vishal
• Hoei Jung-Sheng
• Roohparvar Frankie F

Classifications

• G11C2211/5621

  Physics · mapped topic

• G11C11/5642

  Physics · mapped topic

• G11C27/005

  Physics · mapped topic

• G11C16/28 Primary

  Physics · mapped topic

• G11C2211/5634

  Physics · mapped topic