Memory device for perfoming read operation and program verification operation
US-2024144995-A1 · May 2, 2024 · US
Method for driving semiconductor device
US8976571B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8976571-B2 |
| Application number | US-201113274649-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 17, 2011 |
| Priority date | Oct 20, 2010 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
It is an object to obtain a memory element (DRAM) storing multilevel data easily. The amount of charge accumulated in a capacitor of a memory element (DRAM) is controlled by changing the potential of a wiring (a bit line), which is used for writing data to the memory element (DRAM), in a period in which a transistor included in the memory element (DRAM) is on. Thus, multilevel data stored in the memory element (DRAM) can be obtained without a complex configuration of a semiconductor device including the memory element (DRAM).
First claim
Opening claim text (preview).
The invention claimed is: 1. A method for driving a semiconductor device comprising a word line, a bit line and a memory cell comprising a transistor and a capacitor, wherein a gate of the transistor is electrically connected to the word line, wherein one of a source and a drain of the transistor is electrically connected to the bit line, and wherein the other of the source and the drain of the transistor is electrically connected to a first electrode of the capacitor, the m…
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Electricity · mapped topic
Physics · mapped topic
Physics · mapped topic
Electricity · mapped topic
- G11C11/4094Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US8976571B2 cover?
- It is an object to obtain a memory element (DRAM) storing multilevel data easily. The amount of charge accumulated in a capacitor of a memory element (DRAM) is controlled by changing the potential of a wiring (a bit line), which is used for writing data to the memory element (DRAM), in a period in which a transistor included in the memory element (DRAM) is on. Thus, multilevel data stored in th…
- Who is the assignee on this patent?
- Kamata Koichiro, Semiconductor Energy Lab
- What technology area does this patent fall under?
- Primary CPC classification G11C11/4094. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).