Neural network computation circuit, control circuit therefor, and control method therefor
US-2024411520-A1 · Dec 12, 2024 · US
US8976570B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8976570-B2 |
| Application number | US-201314094532-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 2, 2013 |
| Priority date | Sep 1, 2011 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.
Opening claim text (preview).
The invention claimed is: 1. A memory device, comprising: a storage cell comprising: a selector; an “L” shaped storage component; and an electrode positioned between the selector and the “L” shaped storage component, the electrode electrically coupling the selector and the “L” shaped storage component, the “L” shaped storage component comprising: an approximately vertical portion; a lower approximately horizontal leg portion, wherein the lower approximately horizontal leg…
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