Resistive memory architectures with multiple memory cells per access device

Patent metadata

Field	Value
Publication number	US-8976562-B2
Application number	US-201113292884-A
Country	US
Kind code	B2
Filing date	Nov 9, 2011
Priority date	May 31, 2007
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. A resistive memory structure, comprising:
a plurality of stacked resistive memory cells, each stack including a first and a second resistive memory cell;
a common electrode positioned between the first and second resistive memory cells of a stack and electrically coupling the first and second resistive memory cells to a cell select line; and
a plurality of access devices, each acce…

Assignees

• Liu Jun
• Violette Mike

Inventors

• Liu Jun
• Violette Mike

Classifications

• G11C2213/78

  Physics · mapped topic

• G11C2213/72

  Physics · mapped topic

• G11C13/0026

  Physics · mapped topic

• G11C2213/74

  Physics · mapped topic

• G11C13/0004 Primary

  Physics · mapped topic