Backlight dimmer circuit and backlight dimming method

US8975835B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8975835-B2
Application numberUS-201213807722-A
CountryUS
Kind codeB2
Filing dateNov 25, 2012
Priority dateNov 16, 2012
Publication dateMar 10, 2015
Grant dateMar 10, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

The present invention relates to a backlight dimmer circuit and a backlight dimming method. The backlight dimmer circuit includes a PLL dimming module, which detects a rising edge of a 3D synchronous signal to generate multiple channels of 3D mode dimming signal in phase with the 3D synchronous signal; a phase delay module, which generates time-divided outputs of the multiple channels of 3D mode dimming signal according to a delay set value; an external dimming module, which receives an external dimming signal to generate a 2D mode dimming signal; and a trigger, which receives the 2D mode dimming signal and the multiple channels of 3D mode dimming signal and determines whether to output the 2D mode dimming signal or the multiple channels of 3D mode dimming signal according to a 2D/3D conversion signal.

First claim

Opening claim text (preview).

What is claimed is: 1. A backlight dimmer circuit, comprising: a PLL (Phase-Locked Loop) dimming module, which detects a rising edge of a 3-dimentional (3D) synchronous signal in order to generate multiple channels of a 3D mode dimming signal that are in phase with the 3D synchronous signal, the PLL dimming module further determining a duty ratio of a 3D mode according to an analog dimming direct current (DC) duty; a phase delay module, which receives the multiple channels of th…

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What does patent US8975835B2 cover?
The present invention relates to a backlight dimmer circuit and a backlight dimming method. The backlight dimmer circuit includes a PLL dimming module, which detects a rising edge of a 3D synchronous signal to generate multiple channels of 3D mode dimming signal in phase with the 3D synchronous signal; a phase delay module, which generates time-divided outputs of the multiple channels of 3D mod…
Who is the assignee on this patent?
Shenzhen China Star Optoelect, Shenzhen China Star Optoelctronics Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification H05B33/0809. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).