Semiconductor device reducing risks of a wire short-circuit and a wire flow

US8975760B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8975760-B2
Application numberUS-201213561793-A
CountryUS
Kind codeB2
Filing dateJul 30, 2012
Priority dateAug 10, 2011
Publication dateMar 10, 2015
Grant dateMar 10, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a wiring substrate having a main surface, the wiring substrate including a plurality of first connection pads and a plurality of second connection pads which are formed on the main surface; a first semiconductor chip mounted over the main surface of the wiring substrate, the first semiconductor chip including a plurality of first electrode pads; a second semiconductor chip mounted over the main surface of the wiring sub…

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What does patent US8975760B2 cover?
A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and se…
Who is the assignee on this patent?
Fujiwara Shori, Ps4 Luxco Sarl
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).