Lead-free solder connection structure and solder ball

Patent metadata

Field	Value
Publication number	US-8975757-B2
Application number	US-73605309-A
Country	US
Kind code	B2
Filing date	Mar 3, 2009
Priority date	Mar 5, 2008
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

Solder used for flip chip bonding inside a semiconductor package was a Sn—Pb solder such as a Pb-5Sn composition. Lead-free solders which have been studied are hard and easily form intermetallic compounds with Sn, so they were not suitable for a flip chip connection structure inside a semiconductor package, which requires stress relaxation properties. This problem is eliminated by a flip chip connection structure inside a semiconductor package using a lead-free solder which is characterized by consisting essentially of 0.01-0.5 mass percent of Ni and a remainder of Sn. 0.3-0.9 mass percent of Cu and 0.001-0.01 mass percent of P may be added to this solder composition.

First claim

The invention claimed is:

1. A solder ball which has a diameter of at most 0.1 mm and is made from a lead-free solder consisting of 0.01-0.05 mass percent of Ni, 0.3-0.9 mass percent of Cu, 0.001-0.01 mass percent of P, and a remainder of Sn, the solder having a liquidus temperature of at most 245° C.

2. A solder ball arrangement comprising a plurality of solder balls as claimed in claim 1 disposed on electrodes of a silicon chip.

3. A method of forming a flip chip connection structure comprising disposing a plurality of lead-free solder balls as claimed in claim 1 on electrodes of a silicon chip, heating the solder balls to form them into solder bumps bonded to the electrodes of the silicon chip, placing the silicon chip atop an insulating substrate with the solder bumps aligned with electrodes of the insulating substrate, and heating the solder bumps to bond them to the electrodes of the insulating substrate.

4. A solder ball as claimed in claim 1 wherein the solder contains 0.002-0.005 mass percent of P.

5. A lead-free solder flip chip connection structure for an interior of a semiconductor package comprising a plurality of inner solder bumps sandwiched between and bonded to an Ni-plated electrode of a silicon chip and an Ni-plated electrode on a top surface of an insulating substrate and made of a lead-free solder selected from (a) a solder consisting of 0.01-0.05 mass percent of Ni and a remainder of Sn and having a liquidus temperature of at most 245° C., (b) a solder consisting of 0.01-0.05 mass percent of Ni, 0.3-0.9 mass percent of Cu, and a remainder of Sn and having a liquidus temperature of at most 245° C., and (c) a solder consisting of 0.01-0.05 mass percent of Ni, 0.3-0.9 mass percent of Cu, 0.001-0.01 mass percent of P, and a remainder of Sn and having a liquidus temperature of at most 245° C., the solder bumps being made from solder balls having a diameter of at most 0.1 mm.

6. A lead-free solder flip chip connection structure as claimed in claim 5 wherein the lead-free solder contains 0.3-0.9 mass percent of Cu.

7. A lead-free solder flip chip connection structure as claimed in claim 5 wherein the lead-free solder consists of 0.01-0.05 mass percent of Ni and a remainder of Sn.

8. A lead-free solder flip chip connection structure as claimed in claim 5 wherein the insulating substrate has external electrodes formed on a bottom surface of the insulating substrate for connection to an external member.

9. A lead-free solder flip chip connection structure as claimed in claim 5 wherein the solder consists of 0.01-0.05 mass percent of Ni, 0.3-0.9 mass percent of Cu, and a remainder of Sn.

10. A lead-free solder flip chip connection structure as claimed in claim 5 wherein the solder consists of 0.01-0.05 mass percent of Ni, 0.3-0.9 mass percent of Cu, 0.001-0.01 mass percent of P, and a remainder of Sn.

11. A lead-free solder flip chip connection structure as claimed in claim 5 wherein the solder consists of 0.02-0.04 mass percent of Ni, 0.3-0.7 mass percent of Cu, and a remainder of Sn.

12. A lead-free solder flip chip connection structure as claimed in 5 wherein the solder contains 0.002-0.005 mass percent of P.

13. A solder ball arrangement comprising a plurality of solder balls which have a diameter of at most 0.1 mm and are disposed on electrodes of a silicon chip and are each made of a lead-free solder selected from (a) a solder consisting of 0.01-0.05 mass percent of Ni and a remainder of Sn and having a liquidus temperature of at most 245° C., (b) a solder consisting of 0.01-0.05 mass percent of Ni, 0.3-0.9 mass percent of Cu, and a remainder of Sn and having a liquidus temperature of at most 245° C., and (c) a solder consisting of 0.01-0.05 mass percent of Ni, 0.3-0.9 mass percent of Cu, 0.001-0.01 mass percent of P, and a remainder of Sn and having a liquidus temperature of at most 245° C.

14. A solder ball arrangement as claimed in claim 13 wherein the electrodes are Ni-plated electrodes.

15. A solder ball arrangement as claimed in claim 13 wherein the lead-free solder contains 0.02-0.05 mass percent of Ni.

16. A solder ball arrangement as claimed in claim 13 wherein the solder consists of 0.01-0.05 mass percent of Ni and a remainder of Sn.

17. A solder ball arrangement as claimed in claim 13 wherein the solder consists of 0.01-0.05 mass percent of Ni, 0.3-0.9 mass percent of Cu, and a remainder of Sn.

18. A solder ball arrangement as claimed in claim 13 wherein the solder consists of 0.01-0.05 mass percent of Ni, 0.3-0.9 mass percent of Cu, 0.001-0.01 mass percent of P, and a remainder of Sn.

19. A solder ball arrangement as claimed in claim 13 wherein the solder consists of 0.02-0.04 mass percent of Ni, 0.3-0.7 mass percent of Cu, and a remainder of Sn.

20. A solder ball arrangement as claimed in 13 wherein the solder contains 0.002-0.005 mass percent of P.

Assignees

• Ueshima Minoru
• Suzuki Masayuki
• Yamanaka Yoshie
• Yoshikawa Shunsaku
• Yamaki Tokuro
• Ohnishi Tsukasa
• Senju Metal Industry Co

Inventors

• Ueshima Minoru
• Suzuki Masayuki
• Yamanaka Yoshie
• Yoshikawa Shunsaku
• Yamaki Tokuro
• Ohnishi Tsukasa

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title