Chip package for high-count chip stacks

Patent metadata

Field	Value
Publication number	US-8975754-B2
Application number	US-201313764331-A
Country	US
Kind code	B2
Filing date	Feb 11, 2013
Priority date	Feb 11, 2013
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A chip package is described. This chip package includes a substrate having a side at an angle relative to the top and bottom surfaces of the substrate that is between that of a direction parallel to the top and bottom surfaces and that of a direction perpendicular to the top and bottom surfaces (i.e., between 0° and 90°). This side may be configured to couple to a stack of semiconductor dies in which the semiconductor dies are offset from each other in a direction parallel to the top and bottom surfaces so that one side of the stack defines a stepped terrace. For example, the side may include electrical pads. These electrical pads may be coupled to electrical pads on the top surface by through-substrate vias (TSVs) in the substrate. Moreover, the electrical pads on the top surface may be configured to couple to an integrated circuit.

First claim

What is claimed is:

1. A chip package, comprising:
a substrate having a first surface, a second surface and a side, wherein the first surface and the second surface are substantially parallel, and wherein the side is on a plane which is at an angle relative to a plane of the first surface, wherein the angle is between zero and 90 degrees;
first electrical pads disposed on the first surface;
second electrical pads disposed on the side; and
through-substrate vias (TSVs) electr…

Assignees

• Oracle Int Corp

Inventors

• Thacker Hiren D
• Cunningham John E
• Krishnamoorthy Ashok V

Classifications

• H10W90/724

  Electricity · mapped topic

• H10W90/24

  Electricity · mapped topic

• H10W90/22

  Electricity · mapped topic

• H10W72/823

  Electricity · mapped topic

• H10W70/698

  Electricity · mapped topic