Vias in porous substrates

Patent metadata

Field	Value
Publication number	US-8975751-B2
Application number	US-201113092495-A
Country	US
Kind code	B2
Filing date	Apr 22, 2011
Priority date	Apr 22, 2011
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.

First claim

The invention claimed is:

1. A microelectronic unit, comprising:
a semiconductor substrate having a front surface and a rear surface remote therefrom and embodying a plurality of active semiconductor devices therein, the substrate having a plurality of conductive pads exposed at the front surface and a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, with at least m openings spaced apart in a first direction along the rear surface and n openings spaced apart in a second direction along the rear surface transverse to the first direction, each of m and n being greater than 1;
first and second conductive vias electrically connected with respective first and second pads of the plurality of conductive pads;
pluralities of first and second conductive interconnects extending within respective first and second subsets of the openings, each first conductive interconnect connected to the first conductive via, each second conductive interconnect connected to the second conductive via, the pluralities of first and second conductive interconnects being made of metal; and
first and second conductive contacts exposed at the rear surface for interconnection with an external element, the first and second conductive contacts being electrically connected to the first and second conductive interconnects, respectively, the first and second subsets of the openings underlying the respective first and second conductive contacts, at least one of the openings of the first or second subset having a void located therein and being devoid of the first and second conductive interconnects,
wherein the plurality of first conductive interconnects is separated from the plurality of second conductive interconnects in a horizontal direction substantially parallel to the front surface by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating dielectric material.

2. A microelectronic unit as claimed in claim 1 , wherein each conductive interconnect includes a portion extending in a vertical direction substantially perpendicular to the front surface, the plurality of first conductive interconnects being separated from one another in the horizontal direction by material of the semiconductor substrate.

3. A microelectronic unit as claimed in claim 1 , wherein each conductive interconnect has a width in the horizontal direction of 5 microns or less.

4. A microelectronic unit as claimed in claim 1 , wherein each conductive via has a frusto-conical shape.

5. A microelectronic unit as claimed in claim 1 , wherein the first and second conductive contacts are aligned in a vertical direction substantially perpendicular to the front surface with the respective pluralities of first and second conductive interconnects.

6. A microelectronic unit as claimed in claim 1 , wherein each pad has a top surface exposed at the front surface and a bottom surface remote from the top surface, and the first and second conductive vias extend through the respective first and second pads from the bottom surface to the top surface thereof.

7. A microelectronic unit as claimed in claim 1 , wherein the first and second conductive vias does not extend through the respective first and second pads.

8. A microelectronic unit as claimed in claim 1 , further comprising at least one aperture, each aperture extending from two or more of the openings to at least a bottom surface of a respective one of the pads, wherein the first and second conductive vias extends within respective first and second apertures of the at least one aperture.

9. A microelectronic unit as claimed in claim 1 , wherein the first and second conductive vias include doped semiconductor material.

10. A microelectronic unit as claimed in claim 1 , wherein the first and second conductive vias are directly connected to the first and second pads, respectively.

11. A microelectronic unit as claimed in claim 1 , wherein the first and second conductive vias are electrically connected with the respective first and second pads through intermediate conductive structure extending therebetween.

12. A system comprising a structure according to claim 1 and one or more other electronic components electrically connected to the structure.

13. A system as claimed in claim 12 , further comprising a housing, said structure and said other electronic components being mounted to said housing.

14. A microelectronic unit, comprising:
a semiconductor substrate having a front surface and a rear surface remote therefrom and embodying a plurality of active semiconductor devices therein, the substrate having a plurality of conductive pads exposed at the front surface and a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, with at least m openings spaced apart in a first direction along the rear surface and n openings spaced apart in a second direction along the rear surface transverse to the first direction, each of m and n being greater than 1;
first and second conductive vias electrically connected with respective first and second pads of the plurality of conductive pads;
pluralities of first and second conductive interconnects extending within respective first and second subsets of the openings, each first conductive interconnect connected to the first conductive via, each second conductive interconnect connected to the second conductive via, the pluralities of first and second conductive interconnects being made of metal; and
first and second conductive contacts exposed at the rear surface for interconnection with an external element, the first and second conductive contacts being electrically connected to the first and second conductive interconnects, respectively, the first and second subsets of the openings underlying the respective first and second conductive contacts, at least one of the openings of the first or second subset having a void located therein, the at least one of the openings having the void located therein being partially filled with an insulating dielectric material,
wherein the plurality of first conductive interconnects is separated from the plurality of second conductive interconnects in a horizontal direction substantially parallel to the front surface by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating dielectric material.

15. A microelectronic unit as claimed in claim 14 , wherein the void is located between the dielectric material and a bottom surface of the at least one of the openings, the bottom surface being remote from the rear surface.

16. A microelectronic unit as claimed in claim 14 , wherein each conductive interconnect includes a portion extending in a vertical direction substantially perpendicular to the front surface, the plurality of first conductive interconnects being separated from one another in the horizontal direction by material of the semiconductor substrate.

17. A microelectronic unit as claimed in claim 14 , wherein each conductive interconnect has a width in the horizontal direction of 5 microns or less.

18. A microelectronic unit as claimed in claim 14 , wherein each conductive via has a frusto-conical shape.

19. A microelectronic unit as claimed in claim 14 , wherein the first and second conductive contacts are aligned in a vertical direction substantially perpendicular to the front surface with the respective pluralities of first and second conductive interconnects.

Assignees

• Mohammed Ilyas
• Haba Belgacem
• Uzoh Cyprian
• Savalia Piyush
• Tessera Inc

Inventors

• Mohammed Ilyas
• Haba Belgacem
• Uzoh Cyprian
• Savalia Piyush

Classifications

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title