Microelectronic assemblies with inductors in direct bonding regions
US-2024355768-A1 · Oct 24, 2024 · US
Bias circuit and method of manufacturing the same
US8975725B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975725-B2 |
| Application number | US-200913129344-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 1, 2009 |
| Priority date | Dec 4, 2008 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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- Title
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Abstract
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A bias circuit according to the present invention includes a resistor layer 2 which is placed above a substrate 1 and connected to a ground potential, and a conductor 4 for forming an inductor 5 placed above the resistor layer 2 . Further, a manufacturing method of the bias circuit according to the present invention generates the resistor layer 2 above the substrate 1 and is connected to the ground potential, and generates the conductor 4 for forming the inductor 5 above the resistor layer 2 . The present invention can provide a bias circuit and a manufacturing method of the bias circuit that enables easy integration on a semiconductor substrate and prevents parasitic oscillation.
First claim
Opening claim text (preview).
The invention claimed is: 1. A high frequency amplifier comprising: an FET amplifying a high frequency signal supplied to a gate and outputting an amplified high frequency signal from a drain; a first bias circuit supplying a gate bias to the gate of the FET; and a second bias circuit supplying a drain bias to the drain of the FET, wherein each of the first bias circuit and the second bias circuit comprise: a resistor layer that is placed over a substrate and connected to a…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8975725B2 cover?
- A bias circuit according to the present invention includes a resistor layer 2 which is placed above a substrate 1 and connected to a ground potential, and a conductor 4 for forming an inductor 5 placed above the resistor layer 2 . Further, a manufacturing method of the bias circuit according to the present invention generates the resistor layer 2 above the substrate 1 and is connec…
- Who is the assignee on this patent?
- Hamada Yasuhiro, Kishimoto Shuya, Maruhashi Kenichi, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/497. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).