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Semiconductor device having a thick gate insulating film covering bird's beak region
US8975710B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975710-B2 |
| Application number | US-201313966476-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 14, 2013 |
| Priority date | Sep 24, 2009 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by film thickness fluctuation of the field insulating film, etching fluctuation of the relatively thick gate insulating film, and impurity concentration fluctuation at both sides of the channel due to the inversion-preventing diffusion layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a first MOS transistor having a relatively thick gate insulating film in contact with a substrate surface; and a second MOS transistor in an active region having a relatively thin gate insulating film in contact with a channel region and a gate electrode in contact with the relatively thin gate insulating film, the relatively thick gate insulating film having a thickness greater than a thickness of the relatively thin gat…
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Inventors
Classifications
Electricity · mapped topic
- H10D84/0144Primary
Electricity · mapped topic
Electricity · mapped topic
- H10D84/83Primary
Electricity · mapped topic
- H01L27/088Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8975710B2 cover?
- By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by fi…
- Who is the assignee on this patent?
- Seiko Instr Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0144. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).