Semiconductor device and method of manufacturing the same
US-2024290791-A1 · Aug 29, 2024 · US
Semiconductor device with reduced contact resistance and method of manufacturing thereof
US8975708B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975708-B2 |
| Application number | US-201313915221-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 11, 2013 |
| Priority date | Jul 22, 2010 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Abstract
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A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; and a field-effect transistor (FET) structure formed on the substrate, the FET structure comprising, a gate stack including a gate dielectric and a gate electrode, a first source/drain (S/D) region and a second S/D region each of a second conductivity type, each of the S/D regions having a contact region including metal silicide disposed therein, a segregation r…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8975708B2 cover?
- A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interfac…
- Who is the assignee on this patent?
- Globalfoundries Sg Pte Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/601. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).