Semiconductor device and method of fabricating the same
US-2024014287-A1 · Jan 11, 2024 · US
Method of trimming spacers and semiconductor structure thereof
US8975673B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975673-B2 |
| Application number | US-201213447311-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 16, 2012 |
| Priority date | Apr 16, 2012 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor structure, comprising: a substrate; a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface; a silicon carbon nitride spacer surrounding and contacting the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface; and a silicon oxide spacer surrounding the silicon carbon nitride spacer, wherein the silicon oxide spacer has an L-shape p…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D64/671Primary
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8975673B2 cover?
- A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spac…
- Who is the assignee on this patent?
- Chou Shyan-Liang, Kuo Tsung-Min, Su Po-Wen, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10D64/671. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).