Method for forming source/drain contacts
US-2024379814-A1 · Nov 14, 2024 · US
Super junction trench metal oxide semiconductor device and method of making the same
US8975153B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975153-B2 |
| Application number | US-201313866102-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 19, 2013 |
| Priority date | Mar 14, 2013 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Abstract
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A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for forming a semiconductor device, comprising: forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type; forming a plurality of trenches in the hard mask layer and extending into the substrate, each trench having at least one side wall and a bottom wall, the plurality of trenches being substantially parallel to each other; forming at least one barrier insulator layer along the at least one side…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D84/0133Primary
Electricity · mapped topic
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- What does patent US8975153B2 cover?
- A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the a…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0133. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).