Methods of reducing substrate dislocation during gapfill processing

Patent metadata

Field	Value
Publication number	US-8975152-B2
Application number	US-201213669184-A
Country	US
Kind code	B2
Filing date	Nov 5, 2012
Priority date	Nov 8, 2011
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and may include two adjacent trenches of unequal width separated by an unetched portion of the substrate. The methods may include forming a layer of dielectric material on the substrate. The dielectric material may form a layer in the trenches located adjacent to each other of substantially equivalent height on both sides of the unetched portion of the substrate separating the two trenches. The methods may include densifying the layer of dielectric material so that the densified dielectric within the two trenches of unequal width exerts a substantially similar stress on the unetched portion of the substrate that separates them.

First claim

What is claimed is:

1. A method of forming a layer of dielectric material on a patterned semiconductor substrate, the method comprising:
etching a plurality of trenches on a semiconductor substrate, wherein the plurality of trenches includes two trenches that are of unequal width and are located adjacent to each other such that an unetched portion of the substrate separates the two trenches of unequal width;
forming a layer of dielectric material on the semiconductor substrate,…

Assignees

• Applied Materials Inc

Inventors

• Hong Sukwon
• Hamana Hiroshi
• Liang Jingmei

Classifications

• H10P14/69215 Primary

  Electricity · mapped topic

• H10P14/6529

  Electricity · mapped topic

• H10P14/6522

  Electricity · mapped topic

• H10P14/6336

  Electricity · mapped topic

• H10W10/0143

  Electricity · mapped topic