Semiconductor device and method for forming the same
US-2024395669-A1 · Nov 28, 2024 · US
Dual work function FinFET structures and methods for fabricating the same
US8975141B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975141-B2 |
| Application number | US-201213563202-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 31, 2012 |
| Priority date | Jul 31, 2012 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a dual-workfunction FinFET structure, comprising: depositing an n-type workfunction material in a layer over a plurality of gate structures of each a PMOS and an NMOS and in a plurality of trenches between said gate structures; depositing a low-resistance material layer over the n-type workfunction material layer; depositing a deep ultraviolet light-absorbing oxide (DUOS material layer over the plurality of gate structures of the…
Assignees
Inventors
Classifications
- H10D84/0193Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10B10/00Primary
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8975141B2 cover?
- A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The met…
- Who is the assignee on this patent?
- Wei Andy C, Yang Bin, Tambwe Francis M, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0193. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).