Manufacturing method of substrate structure

US8973258B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8973258-B2
Application numberUS-201213600222-A
CountryUS
Kind codeB2
Filing dateAug 31, 2012
Priority dateJul 2, 2012
Publication dateMar 10, 2015
Grant dateMar 10, 2015

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  5. First independent claim

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Abstract

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A manufacturing method of substrate structure is provided. A base material having a core layer, a first patterned copper layer, a second patterned copper layer and at least one conductive via is provided. The first and second patterned copper layers are respectively located on a first surface and a second surface of the core layer. The conductive via passes through the core layer and connects the first and second patterned copper layers. A first and a second solder mask layers are respectively formed on the first and second surfaces. Portions of the first and second patterned copper layers are exposed by the first and second solder mask layers, respectively. A first gold layer is formed on the first and second patterned copper layers exposed by the first and second solder mask layers. A nickel layer and a second gold layer are successively formed on the first gold layer.

First claim

Opening claim text (preview).

What is claimed: 1. A manufacturing method of a substrate structure, comprising: providing a base material, the base material has a core layer, a first patterned copper layer, a second patterned copper layer and at least one of a conductive via, wherein the core layer has a first surface and a second surface opposite to each other, the first patterned copper layer and the second patterned copper layer are respectively located on the first surface and the second surface, and the co…

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What does patent US8973258B2 cover?
A manufacturing method of substrate structure is provided. A base material having a core layer, a first patterned copper layer, a second patterned copper layer and at least one conductive via is provided. The first and second patterned copper layers are respectively located on a first surface and a second surface of the core layer. The conductive via passes through the core layer and connects t…
Who is the assignee on this patent?
Chen Ching-Sheng, Subtron Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/095. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).