Allocation and control unit for controlling parallel execution of threads on auxiliary processing units

Patent metadata

Field	Value
Publication number	US-8973009-B2
Application number	US-201013202945-A
Country	US
Kind code	B2
Filing date	Feb 22, 2010
Priority date	Feb 24, 2009
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

An allocation and control unit for allocating execution threads for a task to a plurality of auxiliary processing units and for controlling the parallel execution of said execution threads by said auxiliary processing units, the task being executed in a sequential manner by a main processing unit. The allocation and control unit includes means for managing auxiliary logical processing units, means for managing auxiliary physical processing units each corresponding to an auxiliary processing unit, and means for managing the auxiliary processing units. The means for managing the auxiliary processing units include means for allocating an auxiliary logical processing unit to an execution thread to be executed, and means for managing the correspondence between the auxiliary logical processing units and the auxiliary physical processing units. The auxiliary processing units execute in parallel the execution threads for the task by way of the auxiliary logical processing units, which are allocated as late as possible and freed as early as possible.

First claim

The invention claimed is:

1. A processor comprising a main processing unit, a plurality of auxiliary processing units, and an allocation and control unit for allocating execution threads for a task to the plurality of auxiliary processing units, wherein the task is associated with an executable code having a predetermined data dependency graph, said executable code being previously separated, at compilation time, into processing code to be executed on the auxiliary processing units and control code to be executed by the main processing unit, said control code comprising instructions for execution on the auxiliary processing units based on the data dependency graph, the control code of the task being executed in a sequential manner by the main processing unit, wherein each auxiliary processing units corresponds to one of a plurality of physical auxiliary processing units, and each physical auxiliary processing units being associated with one or more of logical auxiliary processing units, wherein the allocation and control unit controls parallel execution of said execution threads by said physical auxiliary processing units via the logical auxiliary processing units, the allocation and control unit comprising:
an auxiliary processing units manager for managing the plurality of auxiliary processing units,
said auxiliary processing units manager being configured to allocate one or more of the logical auxiliary processing units to an execution context identifying an execution thread to be executed from said instructions and to associate each of the plurality of physical auxiliary processing units with said one or more of the logical auxiliary processing units in response to a request for execution of said execution thread on said one or more of the logical auxiliary processing units such that the associated physical auxiliary processing units executes said execution thread for the task,
said auxiliary processing units manager being further configured to free said one or more of the logical auxiliary processing units for said execution context as early as possible in response a freeing request and completion of the execution of the execution thread by said associated physical auxiliary processing units based on the instructions in the control code, and allocate said one or more of the logical auxiliary processing units as late as possible by freeing said one or more of the logical auxiliary processing units in response to a synchronization request and completion of the execution of the execution thread by all of the logical auxiliary processing units specified in said execution context.

2. The unit according to claim 1 ,
wherein said execution context comprises data for identifying the execution thread to be executed, input data for executing the execution thread, and output data.

3. The unit according to claim 1 , wherein said auxiliary processing units manager is configured to:
free, if the request for execution of the execution thread comprises a freeing request, said one or more of the logical auxiliary processing units in response to the execution of said execution thread by the one or more of the physical auxiliary processing units, and
free, if the request for execution of the execution thread comprises a synchronization request and said instructions comprise synchronization data identifying a set of logical auxiliary processing units including said one or more of the logical auxiliary processing units, said one or more of the logical auxiliary processing units in response to the completion of the execution by all of the logical auxiliary processing units specified in the synchronization data.

4. The unit according to claim 2 , wherein said instructions are implemented in the form of an execution pipeline or of a microprogrammed sequencer.

5. The unit according to claim 1 , wherein said auxiliary processing units manager comprises a manager for managing the logical auxiliary processing units, said manager for managing the logical auxiliary processing units being configured to:
provide a free logical auxiliary processing unit identifier;
free a logical auxiliary processing unit; or
associate the one or more of the logical auxiliary processing units with one or more of the plurality of physical auxiliary processing units.

6. The unit according to claim 5 , wherein said manager for managing the logical auxiliary processing units is further configured to select an identifier of a first element of a list of free logical auxiliary processing units to provide the free logical auxiliary processing unit identifier.

7. The unit according to claim 1 , wherein said auxiliary processing units manager comprises a manager for managing the plurality of physical auxiliary processing units, said manager for managing the plurality of physical auxiliary processing units being configured to:
provide a free physical auxiliary processing unit identifier;
associate the one or more of the physical auxiliary processing units with the one or more of the logical auxiliary processing units;
provide an identifier of the one or more of the logical auxiliary processing units associated with each of the plurality of physical auxiliary processing units; or
free one or more of the plurality of physical auxiliary processing units.

8. The unit according to claim 6 , wherein said auxiliary processing units manager is configured to allocate the one or more of the logical auxiliary processing units to the execution thread to be executed by:
searching for a free logical auxiliary processing unit;
allocating the free logical auxiliary processing unit to the execution thread; or
providing an identifier of the free logical auxiliary processing unit allocated to the execution thread.

9. The unit according to claim 1 , further comprising a manager for managing execution contexts on said one or more of the logical auxiliary processing units.

10. The unit according to claim 1 , further comprising an interruption decoder for decoding interrupts coming from the plurality of auxiliary processing units.

11. The unit according to claim 1 , further comprising a manager for managing execution contexts on the main processing unit.

12. The unit according to claim 1 , further comprising a bank of local registers including:
a register for masking exceptions interrupts from the plurality of auxiliary processing units;
a register indicating the plurality of physical auxiliary processing units undergoing execution;
a register indicating said one or more of the logical auxiliary processing units undergoing execution; or
a register indicating said one or more of the logical auxiliary processing units that have not formed the subject of a synchronization request by the task.

Assignees

• Louise Stéphane
• David Vincent
• David Raphael
• Commissariat Energie Atomique

Inventors

• Louise Stéphane
• David Vincent
• David Raphael

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F9/5066 Primary

  Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451) · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title