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US-2024422006-A1 · Dec 19, 2024 · US
Circuit arrangement for execution planning in a data processing system
US8973006B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8973006-B2 |
| Application number | US-201213609795-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 11, 2012 |
| Priority date | Sep 27, 2011 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
Official abstract text for this publication.
A circuit arrangement and method for a data processing system for executing a plurality of tasks with a central processing unit having a processing capacity allocated to the processing unit; the circuit arrangement being configured to allocate the processing unit to the specific tasks in a time-staggered manner for processing, so that the tasks are processed in an order to be selected and tasks not having a current processing request are skipped over in the order during the processing; the circuit arrangement including a prioritization order control unit to determine the order in which the tasks are executed; and in response to each selection of a task for processing, the order of the tasks being redetermined and the selection being controlled so that for a number N of tasks, a maximum of N time units elapse until an active task is once more allocated processing capacity by the processing unit.
First claim
Opening claim text (preview).
What is claimed is: 1. A circuit arrangement for a data processing system for executing a plurality of tasks using a central processing unit with a processing capacity, comprising: a circuit configured to allocate the processing unit to specific tasks in a time-staggered manner for processing, so that the tasks are processed in an order to be selected and tasks not having a current processing request are skipped over in the order during the processing, wherein: the circuit includ…
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- G06F9/4881Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8973006B2 cover?
- A circuit arrangement and method for a data processing system for executing a plurality of tasks with a central processing unit having a processing capacity allocated to the processing unit; the circuit arrangement being configured to allocate the processing unit to the specific tasks in a time-staggered manner for processing, so that the tasks are processed in an order to be selected and tasks…
- Who is the assignee on this patent?
- Boehl Eberhard, Bartholomae Ruben, Bosch Gmbh Robert
- What technology area does this patent fall under?
- Primary CPC classification G06F9/4881. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).