Down-sampling clock and data recovery circuit having selectable rate and phase output and method of operation thereof

Patent metadata

Field	Value
Publication number	US-8971718-B2
Application number	US-201213486552-A
Country	US
Kind code	B2
Filing date	Jun 1, 2012
Priority date	Jun 1, 2012
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.

First claim

What is claimed is:

1. A clock and data recovery (CDR) circuit, comprising:
a line rate CDR circuit having a voltage controlled oscillator, said line rate CDR circuit configured to recover a raw data stream at a receiving line rate;
a fixed-rate down-sampler coupled to said line rate CDR circuit and configured to down-sample said raw data stream based on a fixed-rate; and
a variable-rate down-sampler coupled to said fixed-rate down-sampler and configured further to down-sample said raw data sample based on a variable-rate.

2. The CDR circuit as recited in claim 1 wherein said voltage controlled oscillator is controlled by a frequency tracking control loop and a phase tracking control loop.

3. The CDR circuit as recited in claim 2 wherein said line rate CDR circuit includes a loop switch/power control block configured to power down unused blocks of said phase tracking loop when said frequency tracking loop controls said voltage controlled oscillator and power down unused blocks of said frequency tracking loop when said phase tracking loop controls said voltage controlled oscillator.

4. The CDR circuit as recited in claim 1 wherein said voltage controlled oscillator has an active differential capacitor bank.

5. The CDR circuit as recited in claim 1 wherein said fixed-rate down-sampler has a selectable phase.

6. The CDR circuit as recited in claim 1 wherein said variable-rate down-sampler has a selectable phase and sampling rate.

7. The CDR circuit as recited in claim 1 wherein said fixed-rate down-sampler includes a multiphase generator having a counter.

8. The CDR circuit as recited in claim 1 wherein said variable-rate down-sampler includes a preload binary counter configured to produce n+1 divide-by-2 n rate clock outputs.

9. A method of recovering a clock and data from a received raw data stream, comprising:
recovering a raw data stream at a receiving line rate using a voltage controlled oscillator;
initially down-sampling said raw data stream based on a fixed rate; and
further down-sampling said raw data sample based on a variable rate.

10. The method as recited in claim 9 wherein said voltage controlled oscillator is controlled by a frequency tracking control loop and a phase tracking control loop.

11. The method as recited in claim 10 wherein said recovering comprises:
powering down unused blocks of said phase tracking loop when said frequency tracking loop controls said voltage controlled oscillator; and
powering down unused blocks of said frequency tracking loop when said phase tracking loop controls said voltage controlled oscillator.

12. The method as recited in claim 9 wherein said voltage controlled oscillator has an active differential capacitor bank.

13. The method as recited in claim 9 wherein said initially down-sampling is carried out at a selectable phase.

14. The method as recited in claim 9 wherein said further down-sampling is carried out at a selectable phase and sampling rate.

15. The method as recited in claim 9 wherein said initially down-sampling comprises employing a multiphase generator having a counter.

16. The method as recited in claim 9 wherein said further down-sampling comprises employing a preload binary counter configured to produce n+1 divide-by-2 n rate clock outputs.

17. A BI-PON optical network transceiver (ONT) receiver front-end, comprising:
a clock and data recovery (CDR) circuit, including:
a line rate CDR circuit having a voltage controlled oscillator, said line rate CDR circuit configured to recover a raw data stream at a receiving line rate,
a fixed-rate down-sampler coupled to said line rate CDR circuit and configured to down-sample said raw data stream based on a fixed rate, and
a variable-rate down-sampler coupled to said fixed-rate down-sampler and configured further to down-sample said raw data sample based on a variable rate.

18. The receiver front-end as recited in claim 17 wherein said voltage controlled oscillator is controlled by a frequency tracking control loop and a phase tracking control loop.

19. The receiver front-end as recited in claim 18 wherein said line rate CDR circuit includes a loop switch/power control block configured to power down unused blocks of said phase tracking loop when said frequency tracking loop controls said voltage controlled oscillator and power down unused blocks of said frequency tracking loop when said phase tracking loop controls said voltage controlled oscillator.

20. The receiver front-end as recited in claim 17 wherein said voltage controlled oscillator has an active differential capacitor bank.

21. The receiver front-end as recited in claim 17 wherein said fixed-rate down-sampler has a selectable phase.

22. The receiver front-end as recited in claim 17 wherein said variable-rate down-sampler has a selectable phase and sampling rate.

23. The receiver front-end as recited in claim 17 wherein said fixed-rate down-sampler includes a multiphase generator having a counter.

24. The receiver front-end as recited in claim 17 wherein said variable-rate down-sampler includes a preload binary counter configured to produce n+1 divide-by-2 n rate clock outputs.

Assignees

• Chow Hungkei
• Suvakovic Dusan
• Van Praet Christophe
• Torfs Guy
• Yin Xin
• Li Zhisheng
• Alcatel Lucent

Inventors

• Chow Hungkei
• Suvakovic Dusan
• Van Praet Christophe
• Torfs Guy
• Yin Xin
• Li Zhisheng

Classifications

• Y02B60/31

  Cross-Sectional Technologies · mapped topic

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H04L7/0337 Primary

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L25/06

  DC level restoring means; Bias distortion correction {; Decision circuits providing symbol by symbol detection} · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title