Method and devices for memory cell erasure with a programming monitor of reference cells

US8971121B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8971121-B2
Application numberUS-201313971075-A
CountryUS
Kind codeB2
Filing dateAug 20, 2013
Priority dateMay 27, 2008
Publication dateMar 3, 2015
Grant dateMar 3, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for operating an array of memory cells, the method comprising: erasing a selected group of memory cells that includes a number of reference cells and a number of data cells; performing a programming monitor operation on the number of erased reference cells; and determining a number of operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of er…

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Next steps

Free tools are coming soon. Tell us what you want to track and we'll notify you.

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US8971121B2 cover?
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification G11C16/06. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).