Threshold voltage calibration using reference pattern detection

US8971111B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8971111-B2
Application numberUS-201313900718-A
CountryUS
Kind codeB2
Filing dateMay 23, 2013
Priority dateMay 23, 2013
Publication dateMar 3, 2015
Grant dateMar 3, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A V T offset error differential is calculated. The V T offset error differential is a difference between a number of errors of the predominant type at a first V T offset and a number of errors of the predominant type at a second V T offset. A V T offset is determined using a ratio of the error type differential and the V T offset error differential.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: identifying a predominant type of error of a memory unit of solid state memory cells; calculating an error type differential, the error type differential comprising a difference between a number of charge loss errors and a number of charge gain errors of the memory unit; calculating a V T offset error differential, the V T offset error differential comprising a difference between a number of errors of the predominant type at a fir…

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Next steps

Free tools are coming soon. Tell us what you want to track and we'll notify you.

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US8971111B2 cover?
A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A V T offset error differential is calculated. The V T offset error differential is a difference between a num…
Who is the assignee on this patent?
Seagate Technology Llc
What technology area does this patent fall under?
Primary CPC classification G11C16/3404. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).