Memory programming to reduce thermal disturb

US8971104B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8971104-B2
Application numberUS-201213530732-A
CountryUS
Kind codeB2
Filing dateJun 22, 2012
Priority dateJun 22, 2012
Publication dateMar 3, 2015
Grant dateMar 3, 2015

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Abstract

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A resistive memory array is programmed such that particular adjacent pairs of memory cells along a bit line having a back-to-back relationship are programmed together. The memory cells having the back-to-back relationship share a continuous chalcogenide material and a SiN material.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for programming a data word to an array of memory cells, wherein the array of memory cells comprise a first memory cell, a second memory cell that is adjacent to the first memory cell in a first direction along an axis, and a third memory cell that is adjacent to the first memory cell in a second direction along the axis, wherein the first direction is opposite to the second direction and the first memory cell is more thermally insulated from the sec…

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What does patent US8971104B2 cover?
A resistive memory array is programmed such that particular adjacent pairs of memory cells along a bit line having a back-to-back relationship are programmed together. The memory cells having the back-to-back relationship share a continuous chalcogenide material and a SiN material.
Who is the assignee on this patent?
Redaelli Andrea, Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification G11C13/0004. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).