Neural network computation circuit, control circuit therefor, and control method therefor
US-2024411520-A1 · Dec 12, 2024 · US
US8971104B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8971104-B2 |
| Application number | US-201213530732-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 22, 2012 |
| Priority date | Jun 22, 2012 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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A resistive memory array is programmed such that particular adjacent pairs of memory cells along a bit line having a back-to-back relationship are programmed together. The memory cells having the back-to-back relationship share a continuous chalcogenide material and a SiN material.
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What is claimed is: 1. A method for programming a data word to an array of memory cells, wherein the array of memory cells comprise a first memory cell, a second memory cell that is adjacent to the first memory cell in a first direction along an axis, and a third memory cell that is adjacent to the first memory cell in a second direction along the axis, wherein the first direction is opposite to the second direction and the first memory cell is more thermally insulated from the sec…
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