Wide range multiport bitcell

Patent metadata

Field	Value
Publication number	US-8971096-B2
Application number	US-201313953473-A
Country	US
Kind code	B2
Filing date	Jul 29, 2013
Priority date	Jul 29, 2013
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.

First claim

What is claimed is:

1. A circuit for a memory cell, comprising:
a pair of cross-coupled inverters, wherein a first inverter in the pair is configured to drive a first node for the memory cell and a remaining second inverter in the pair is configured to drive a second node for the memory cell;
a plurality of read ports configured to access the second node;
a first write port including a write word line, a complement write word line, and a write bit line;
a first transmission…

Assignees

• Qualcomm Inc

Inventors

• Jung Changho
• Vattikonda Rakesh
• Desai Nishith
• Yoon Sei Seung

Classifications

• G11C11/419 Primary

  Physics · mapped topic

• G11C8/16

  Physics · mapped topic