Stacked memory with interface providing offset interconnects

Patent metadata

Field	Value
Publication number	US-8971087-B2
Application number	US-201113997148-A
Country	US
Kind code	B2
Filing date	Dec 2, 2011
Priority date	Dec 2, 2011
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

First claim

What is claimed is:

1. A memory device comprising:
a system element for the memory device; and
a memory stack coupled with the system element, the memory stack including one or more memory die layers, each memory die layer including first face and a second face, the second face of each memory die layer including an interface for coupling a plurality of data interface pins of the memory die layer with a plurality of data interface pins in a first face of a coupled element;
wher…

Assignees

• Vogt Pete
• Schaefer Andre
• Morrow Warren
• Halbert John
• Kim Jin
• Shoemaker Kenneth
• Intel Corp

Inventors

• Vogt Pete
• Schaefer Andre
• Morrow Warren
• Halbert John
• Kim Jin
• Shoemaker Kenneth

Classifications

• H10W90/724

  Electricity · mapped topic

• H10W90/722

  Electricity · mapped topic

• H10W90/297

  Electricity · mapped topic

• H10W20/20

  Electricity · mapped topic

• H10W20/212

  Electricity · mapped topic