Self-refresh adjustment in memory devices configured for stacked arrangements

Patent metadata

Field	Value
Publication number	US-8971085-B2
Application number	US-201313964764-A
Country	US
Kind code	B2
Filing date	Aug 12, 2013
Priority date	Dec 13, 2011
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a) a stack position identifier for identifying a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices;
b) a self-refresh oscillator configured to generate an oscillating signal to control a rate of self-refresh operations for the semiconductor memory device; and
c) an oscillator adjustor configured to change a frequency of the oscillating signal…

Assignees

• Iii Holdings 2 Llc

Inventors

• Stephens Jr Michael C

Classifications

• H10W90/722

  Electricity · mapped topic

• G11C7/22

  Physics · mapped topic

• G11C29/028

  Physics · mapped topic

• G11C11/401

  Physics · mapped topic

• G11C7/106

  Physics · mapped topic