Processor and memory communication in a stacked memory system
US-2024411709-A1 · Dec 12, 2024 · US
US8971084B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8971084-B2 |
| Application number | US-201313948914-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 23, 2013 |
| Priority date | Jul 23, 2013 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits.
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What is claimed is: 1. A semiconductor memory cell comprising: a set of circuit structures, each comprising column input/output circuits; and a set of replicas, that are non-functional, corresponding to the column input/output circuits, the set of replicas configured to fill an empty space next to the column input/output circuits, wherein the set of replicas provide context protection for the column input/output circuits. 2. The semiconductor memory cell of…
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