Array substrate, display panel, spliced display panel and display driving method
US-12033571-B2 · Jul 9, 2024 · US
Display driving circuit, display panel and display device
US8970565B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8970565-B2 |
| Application number | US-201013378233-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 18, 2010 |
| Priority date | Jun 17, 2009 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.
First claim
Opening claim text (preview).
The invention claimed is: 1. A display driving circuit including a shift register, said display driving circuit carrying out simultaneous selection of a plurality of signal lines at a given timing, wherein, a stage of the shift register includes (i) a flip-flop of a set-reset type configured to receive an initialization signal and (ii) a signal generating circuit configured to, receive a simultaneous selection signal, and generate an output signal of the stage by use of an outp…
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Physics · mapped topic
Physics · mapped topic
- G11C19/28Primary
Physics · mapped topic
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- What does patent US8970565B2 cover?
- A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetti…
- Who is the assignee on this patent?
- Hachida Takuya, Murakami Yuhichiroh, Furuta Shige, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G11C19/28. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).