Method for creating a 3D stacked multichip module

Patent metadata

Field	Value
Publication number	US-8970047-B2
Application number	US-201414465721-A
Country	US
Kind code	B2
Filing date	Aug 21, 2014
Priority date	Mar 16, 2011
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2 N-1 being less than W and 2 N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2 n-1 landing pads for each mask n=1, 2 . . . N.

First claim

What is claimed is:

1. A method for creating a three-dimensional stacked multichip module comprising:
providing a set of W integrated circuit die, W being an integer greater than 1, each die in the set comprising a patterned conductor layer, the patterned conductor layer comprising an electrical contact region, the electrical contact region comprising landing pads;
mounting a handling die to a selected die in the set, over the patterned conductor layer;
removing an exposed lay…

Assignees

• Macronix Int Co Ltd

Inventors

• Chen Shih-Hung

Classifications

• H10W99/00

  Electricity · mapped topic

• H10W20/0234

  Electricity · mapped topic

• H10W20/2125

  Electricity · mapped topic

• H10W20/0238

  Electricity · mapped topic

• H10W20/0253

  Electricity · mapped topic