NAND type nonvolatile semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-8969998-B2
Application number	US-201113225743-A
Country	US
Kind code	B2
Filing date	Sep 6, 2011
Priority date	Feb 23, 2011
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a semiconductor substrate;
a plurality of element-separating insulators formed in an upper layer portion of the semiconductor substrate, the plurality of element-separating insulators partitioning the upper layer portion into a plurality of active areas of the semiconductor substrate extending in a first direction;
contacts physically connected to the active areas respectively; and
a recess formed in a part, i…

Assignees

• Nishihara Kiyohito
• Toshiba Kk

Inventors

• Nishihara Kiyohito

Classifications

• H10W20/40

  Electricity · mapped topic

• H10W10/0143 Primary

  Electricity · mapped topic

• H10W10/17

  Electricity · mapped topic

• H01L21/76229

  Electricity · mapped topic

• H01L27/11524 Primary

  Electricity · mapped topic