Semiconductor storage device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-8969983-B2
Application number	US-201213425067-A
Country	US
Kind code	B2
Filing date	Mar 20, 2012
Priority date	Jul 11, 2011
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A memory includes a semiconductor substrate. Cell transistors are on the substrate. Contact plugs each of which is buried between the adjacent cell transistors and electrically connected to a diffusion layer between the adjacent cell transistors. An interlayer dielectric film buries gaps between the contact plugs. A storage element is provided not above the contact plugs but above the interlayer dielectric film. A sidewall film covers a part of a side surface of the storage element, and is provided to overlap with one of the contact plugs as viewed from above a surface of the semiconductor substrate. A lower electrode is provided between a bottom of the storage element and the interlayer dielectric film and between the sidewall film and one of the contact plugs, and electrically connects the storage element to one of the contact plugs.

First claim

The invention claimed is:

1. A semiconductor storage device comprising:
a semiconductor substrate;
a plurality of cell transistors on the semiconductor substrate;
a plurality of contact plugs each buried between the adjacent cell transistors, and directly and electrically connected to a diffusion layer between the adjacent cell transistors;
an interlayer dielectric film burying gaps between the plurality of the contact plugs;
a storage element provided not above the contac…

Assignees

• Kanaya Hiroyuki
• Toshiba Kk

Inventors

• Kanaya Hiroyuki

Classifications

• H01L43/12 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L27/226

  Electricity · mapped topic

• H10N50/01 Primary

  Electricity · mapped topic

• H10N50/10

  Electricity · mapped topic