Semiconductor device having semiconductor pillar

US8969975B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8969975-B2
Application numberUS-201313951982-A
CountryUS
Kind codeB2
Filing dateJul 26, 2013
Priority dateAug 8, 2012
Publication dateMar 3, 2015
Grant dateMar 3, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed herein is a device that includes: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including a first insulating pillar that is in contact with the first side surface of the semiconductor pillar; a gate electrode that covers the second side surface of the semiconductor pillar with an intervention of a gate insulating film; a first impurity diffusion layer formed on an upper surface of the semiconductor pillar; a second impurity diffusion layer formed in the active region located below the semiconductor pillar; and an etching protection wall that is arranged to surround the semiconductor pillar.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including a first insulating pillar that is in contact with the first side surface of the semiconductor pillar;…

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What does patent US8969975B2 cover?
Disclosed herein is a device that includes: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including a first insulating pillar that…
Who is the assignee on this patent?
Elpida Memory Inc, Ps4 Luxco Sarl
What technology area does this patent fall under?
Primary CPC classification H10D64/0133. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).