Sub-lithographic semiconductor structures with non-constant pitch
US-2015380262-A1 · Dec 31, 2015 · US
US8969975B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969975-B2 |
| Application number | US-201313951982-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 26, 2013 |
| Priority date | Aug 8, 2012 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Disclosed herein is a device that includes: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including a first insulating pillar that is in contact with the first side surface of the semiconductor pillar; a gate electrode that covers the second side surface of the semiconductor pillar with an intervention of a gate insulating film; a first impurity diffusion layer formed on an upper surface of the semiconductor pillar; a second impurity diffusion layer formed in the active region located below the semiconductor pillar; and an etching protection wall that is arranged to surround the semiconductor pillar.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including a first insulating pillar that is in contact with the first side surface of the semiconductor pillar;…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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