Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
High threshold voltage NMOS transistors for low power IC technology
US8969969B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969969-B2 |
| Application number | US-72731210-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 19, 2010 |
| Priority date | Mar 20, 2009 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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- Title
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Abstract
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Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
First claim
Opening claim text (preview).
Having thus described my invention, what I claim as new and desire to secure by Letters Patent is as follows: 1. An integrated circuit including a plurality of transistors of benchmark design of a first conductivity type, each said transistor of said benchmark design including a stressed layer or film applying stress on a channel of said transistor of benchmark design to cause increased electron mobility in said channel, said stressed film also causing out-diffusion of impurities…
Assignees
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Classifications
Electricity · mapped topic
- H10D84/0167Primary
Electricity · mapped topic
- H10D84/038Primary
Electricity · mapped topic
Electricity · mapped topic
- H01L21/823807Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969969B2 cover?
- Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impur…
- Who is the assignee on this patent?
- Chan Victor W C, Kanike Narasimhulu, Shang Huiling, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0167. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).