Semiconductor device with reduced miller capacitance and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-8969952-B2
Application number	US-201313742320-A
Country	US
Kind code	B2
Filing date	Jan 15, 2013
Priority date	Nov 23, 2012
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A semiconductor power device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth deeper than the junction depth in the ion well; a gate oxide layer in the gate trench; a gate embedded the gate trench; and a pocket doping region in the epitaxial layer. The pocket doping region is adjacent to and covers at least a corner of the gate trench.

First claim

What is claimed is:

1. A power semiconductor device, comprising:
a semiconductor substrate having a first conductivity type;
an epitaxial layer on the semiconductor substrate;
an ion well having a second conductivity type in the epitaxial layer, wherein the ion well has a junction depth;
a gate trench in the epitaxial layer, wherein a depth of the gate trench is greater than the junction depth of the ion well;
a gate oxide layer on interior surface of the gate trench;
a…

Assignees

• Anpec Electronics Corp

Inventors

• Lin Yung-Fa

Classifications

• H10D64/2527

  Electricity · mapped topic

• H10D64/256

  Electricity · mapped topic

• H10D62/393

  Electricity · mapped topic

• H10D62/157

  Electricity · mapped topic

• H10D30/668

  Electricity · mapped topic