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US8969951B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969951-B2 |
| Application number | US-201213470859-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 14, 2012 |
| Priority date | Jun 9, 2011 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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- Title
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Abstract
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The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate having at least two surfaces opposite to each other; a vertical transistor that is formed in the semiconductor substrate, and that has a gate electrode and a source layer at one surface side of the two surface sides of the semiconductor substrate and has a drain layer at the other surface side of the semiconductor substrate; a first interlayer dielectric film formed over the one surface of the…
Assignees
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Classifications
Electricity · mapped topic
- H10P95/90Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969951B2 cover?
- The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as view…
- Who is the assignee on this patent?
- Fukui Yuki, Katou Hiroaki, Renesas Electronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P95/90. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).